Defects are major causes of yield loss for all integrated circuit ("IC") products. The focus of yield improvement efforts is to identify and eliminate major yield limiters. This is done, in part, by scanning a sample of IC wafers with in-line scanners and classifying defects. The most common defect types are identified, after which an effort is made to find the source of these common defects and fix the problem.
Identifying a cause of a defect is usually the most time consuming and costly component of yield improvement efforts. Some defect types are not too difficult to diagnose. Easy to diagnose defects include those caused by particles. Such defects are often still present during in-line inspection. Consequently, the particle composition can be determined by known techniques, such as energy dispersion spectroscopy analysis.
On the other hand, some defect types are difficult to diagnose because they leave their imprint by distorting the physical topography of the water surface. These defects may also no longer be present at a step where inspection can be performed, which makes identification difficult. Examples of such defects can include bubbles and particles in the photoresist layer of the IC. As those skilled in the art will appreciate, diagnosis of defects in the photoresist layer is difficult because photoresist can only be inspected after it is developed. Moreover, bubble and particle defects in the photoresist often do not appear as bubbles or particles after the photoresist is developed, but may take on some other distorted shape or appearance, which further complicates diagnosis.
Because defect diagnosis is difficult if the defects causing a distorted wafer profile are no longer present during inspection, yield learning typically involves running pre-designed experiments. Such experiments commonly involve processing sets of wafers with different fabrication recipes. Often, the number of wafers used in such experiments is limited, however, in order to save material costs. But if too few wafers are used, experimental results may turn out to be inconclusive thus frustrating defect diagnosis and yield improvement. Defect simulation can thus provide guidance for such experimental work by eliminating some of the competing theories about the causes of certain defects.
In addition, submicron lithography defect simulation has been known to provide insight about how defects of different sizes and types can distort expected wafer profiles. Through the use of lithography simulation, defect causes can be identified and verified by comparing the simulation results with observed wafer profiles. Both the insight and data gained from lithography simulation, such as when and how defects cause shorts or opens, and the nature of the distorted patterns the defects cause, can assist in yield improvement efforts.
Topography simulations of photoresist bubbles have been performed using the Metropole lithography simulator developed at Carnegie Mellon University. Among the capabilities of this simulator is a two-dimensional modeling of in-line aerial imaging, exposure of photoresist, and development of photoresist. The quantitative accuracy of the defect simulations was verified by simulating particles of various sizes in the photoresist. Experiments were then performed to recreate the photoresist defects in actual IC wafers. These experimental results were found to correlate and match those from the simulations.
Once the simulator is tuned to the experimental data, it can be used to run further experiments to observe how a wide variety of defects are likely to impact photoresist profiles. The results from simulations of various defects, such as the impact of bubbles and particles in the photoresist and on top of the photoresist layer, can then be employed to determine and correlate simulated defects with observed defects. This has been done for individual defects and for similar groupings of related defect types.
What is needed is a method or technique for cataloging or storing a host of defect simulations that can then be used to diagnose the wide variety of defects encountered in a production environment. The catalog would include entries for known defects, and a profile of the simulated effect of such defect in IC processing. Observed defects could then be matched with the simulated defect effects. Once a match of simulated and observed effects is found, the associated cause of the defect can be readily identified. Such a catalog or library of defect profiles would help cut down the time required to identify the cause of a defect. Moreover, known techniques can then be applied to correct the particular defect identified.